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178
XMEGA A [MANUAL]
8077I–AVR–11/2012
dead time. The high side and low side have independent dead-time setting, and the dead-time registers are double
buffered.
Figure 15-3. Dead-time generator block diagram.
As shown in Figure 15-4 on page 178, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle,
until it reaches zero. A nonzero counter value will force both the low side and high side outputs into their OFF state.
When a change is detected on the WG output, the dead-time counter is reloaded according to the edge of the input. A
positive edge initiates a counter reload of the DTLS register, and a negative edge a reload of DTHS register.
Figure 15-4. Dead-time generator timing diagram.
15.5
Pattern Generation
The pattern generator unit reuses the DTI registers to produce a synchronized bit pattern across the port it is connected
to. In addition, the waveform generator output from compare channel A (CCA) can be distributed to and override all the
port pins. These features are primarily intended for handling the commutation sequence in brushless DC motor (BLDC)
and stepper motor applications. A block diagram of the pattern generator is shown in “Pattern generator block diagram.”
on page 179. For each port pin where the corresponding OOE bit is set, the multiplexer will output the waveform from
CCA.
Dead Time Generator
Edge Detect
BV
DQ
= 0
DTLSBUF
DTLS
DTHSBUF
DTHS
"DTLS"
(To PORT)
"DTHS"
(To PORT)
Counter
EN
LOAD
WG output
"dti_cnt"
"WG output"
"DTLS"
"DTHS"
tDTILS
tDTIHS
T
tP
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